Understanding Phase Noise and Lock Time in PLL Designs

When determining phase noise and lock time, engineers must properly evaluate the transfer function of charge-pump designs.

By: Dean Banerjee, Wireless Applications Engineer, National Semiconductor

Contents
Transfer functions
Transfer function analysis
Additional phase noise factors
Phase noise index
Transfer function analysis
Comparison of two models

When it comes to phased-locked-loop (PLL) design and simulation, there a lot of rules of thumb that can give inaccurate results because they are based on outdated PLL architectures and rough mathematical approximations. In today's days of powerful computers, it becomes easier to visualize and simulate PLL systems in their full beauty and complexity. Two PLL characteristics that are commonly simulated are phase noise and lock time.

Transfer functions
Regardless of loop filter topology or application, the transfer function is key to understanding phase noise and lock time in PLL designs. Figure 1 shows a basic diagram of a charge-pump PLL used as a frequency synthesizer while table 1 shows the basic transfer functions for phase (not frequency) for various noise sources of the PLL.

In the table above, G(s) is used to denote the open loop gain of the system in figure 1 and is given by the formula:

Transfer function analysis
Now that we've laid this groundwork, let's examine the transfer functions in Table 1 and then apply this analysis to the prediction of phase noise. From this brief analysis of transfer functions it will be shown why the N counter value multiplies the phase noise. After this, a modification to the formula that accounts for the noise characteristics of the charge pump will be presented.

If a noise source is introduced at a place described in Table 1, the resulting noise that shows up at the output will be the original noise profile times the transfer function given. Note that all the transfer functions, except for the voltage-controlled oscillator (VCO) have the common factor of:

This factor can be approximated as shown below in figure 2.

Figure 2 illustrates that on frequencies significantly less than the loop bandwidth, the noise source must be approximately multiplied by N. For frequencies much larger than the loop bandwidth, it turns out that the voltage-controlled oscillator (VCO) noise is the dominant noise source. The close-in phase noise voltage is therefore multiplied N, and therefore the phase noise power varies as 20 X log(N), but only if all other factors are held constant.

Additional phase noise factors
In the above analysis, we did not account for several relevant factors. In charge-pump PLL designs, the phase detector noise is not constant, but actually increases as 10 x log(reference frequency). In other words, if the reference frequency is doubled, and the output frequency is held constant, the phase noise improvement is 3 db, not 6 db.

The second factor is that the charge pump noise transfer function is divided by the charge pump gain. This is why many synthesizers perform better in the higher charge pump gain mode. However, this does not necessarily apply to all PLL synthesizers since the charge pump can also be noisier at higher gains. For other synthesizers, the charge pump noise is proportional to the gain, so the phase noise becomes independent of charge pump current.

Phase noise index
In general, the close-in phase noise can be normalized to an N value of 1 and a comparison frequency of 1 Hz. For instance, this phase noise index for the National Semiconductor LMX2330/31/32 family of PLLs is typically -213 dbc/Hz. Thus phase noise can be calculated using:

Phase Noise = (Phase Noise Index) + 20• log(N) + 10• log(Comparison Frequency)

To properly calculate phase noise, the noise profile of the VCO, dividers, crystal reference, charge pump, and even the thermal noise of the resistors in the loop filter need to be known. However, for a charge pump PLL, the charge pump noise typically dominates over the noise from the dividers, resistors, and crystal reference. Therefore, a more sophisticated analysis can be done by multiplying each noise source by its respective transfer function and adding all of the results together. But, simply using the phase noise index is easier and gives a benchmark to compare on PLL synthesizer chip to another.

Figure 3 shows an actual phase noise profile for a PLL. Close to the carrier, the charge pump noise dominates while at frequencies greater than the loop bandwidth, the VCO noise dominates. In this example, the theoretical charge pump noise profile provides a reasonable estimate in this case because the loop bandwidth is sufficiently wide to keep the VCO noise from distorting the close-in phase noise profile.

Transfer function analysis
To apply the transfer function to lock time, the frequency response is considered when the N counter is instantaneously changed. If the PLL was originally at frequency f1, and the new target frequency is f2, then the Laplace transform of this step change in the frequency seen at the phase detector is:

However, since it is the frequency response that is desired (not the phase response), then it is necessary to multiply this by s.

Let's perform a sample calculation. For a third order passive filter, the transfer function can be calculated using:

Note that the zeroes of the denominator are the poles of the closed-loop transfer function. Since this is a fourth order polynomial, the zeroes of this function can be found analytically, although it is much easier to find them numerically. At least two of these poles will be complex, and they will be close to two of the poles of the second order approximation. The transfer function can be rewritten as:

Finally, this leads to the transient response. Note that although some of the coefficients Ai will be complex, they will combine in such a way that the final solution is real. Since the poles need to be calculated for real final solution, it will be assumed that they all have negative real parts. If this is not the case, then the design is unstable. So, assuming a stable system, the transient response is:

Comparison of two models
Table 2 describes the response of a PLL using both the classical model that disregards the terms in the transfer function, and the model that accounts for the pole and all four zeros of the transfer function. Note that in the real world, lock time is often longer than theoretically predicted if the VCO tuning constant is non-linear, or the PLL tuning voltage gets too close to the supply rails.

Conclusion
The PLL transfer function is an important tool to understanding phase noise and lock time. With the vast amount of computational software available today, such as Mathcad, sophisticated and mathematically rigorous PLL models become more practical to implement. Although these models are only as good as the assumptions that went into them, they can reduce unnecessary circuit tinkering and debugging caused by mathematical approximations and rough rules of thumb.

References
1. Banerjee, Dean, PLL Performance, Simulation, and Design, Copyright 1998, 1999 National Semiconductor.
2. Banerjee, Dean, EasyPLL Program, Copyright 1998, 1999 National Semiconductor
3. Banerjee, Dean, Miscellaneous PLL Models
4. Gardner, F.M., Phased-Locked Loop Techniques, 2nd ed., John Wiley & Sons, 1980

About the author
Dean Banerjee, Wireless Applications Engineer National Semiconductor Corp., 1090 Kifer Rd. MS 16-177, Sunnyvale, CA 94086. Phone: 408-721-3319, Fax: 408-721-5559.