Ultralow Jitter Clock Generation (4.5GHz) & Clock Distribution (7.5GHz) Family

Analog Devices recently announced the LTC6952, LTC6953, LTC6955 and LTC6955-1 family of low jitter, high performance clock generation and distribution devices supporting JESD204B subclass 1 clocking applications up to 7.5GHz. These products are ideal for high-speed data converter clocking applications, with a scalable architecture to provide thousands of synchronized low jitter clocks, each with a complementary SYSREF signal.

• LTC6952: ultralow jitter, 4.5GHz PLL with 11 outputs and JESD204B support
• LTC6953: ultralow jitter, 4.5GHz clock distributor with 11 outputs and JESD204B support
• LTC6955: ultralow jitter, 7.5GHz, 11 output fanout buffer
• LTC6955-1: LTC6955 with additional ÷2 on one output

The LTC6952 is a high performance, ultralow jitter, JESD204B clock generation and distribution device. It includes a phase locked loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The LTC6952’s eleven outputs can be configured as up to five JESD204B subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply 11 general purpose clock outputs for non-JESD204B applications. Each output has its own individually programmable frequency divider and output driver. All outputs can be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays.

The LTC6953 is the clock distribution function of the LTC6952. The LTC6955 is an 11 output fanout buffer with a parallel interface that selects one of three states per output group: in-phase, 180° out of phase, or power-down. The LTC6955-1 is the same as the LTC6955-1 except one output has an integrated ÷2.

• View the product pages, download data sheet, order samples and evaluation boards on Analog.com:
  • LTC6952: www.analog.com/ltc6952
  • LTC6953: www.analog.com/ltc6953
  • LTC6955: www.analog.com/ltc6955
  • LTC6955-1: www.analog.com/ltc6955

All devices are offered in a 52-lead, 7 mm × 8 mm plastic QFN package. The device is rated for operation from –40°C to 125°C junction temperature. Unused outputs can be powered down when not in use. Samples and evaluation board of all products are available immediately. Production quantities of all products will be available by the end of June.

The LTC6952 and LTC6955-1 will be demonstrated at IMS 2018, booth 1725, on June 12-14 in Philadelphia. The demo will show a scalable architecture for thousands of outputs.

• LTC6952
  • JESD204B Subclass 1 SYSREF Signal Generation
  • Low Noise Integer-N PLL
  • Max. RF Frequency: 4.5GHz
  • Normalized In-Band Phase Noise Floor: -229dBc/Hz
  • Normalized In-Band 1/f Noise: -281dBc/Hz
  • Eleven Independent, Low Noise Outputs with Programmable Coarse Digital & Fine Analog Delays
  • Additive Output Jitter: <6fs_RMS (12kHz – 20MHz; 4.5GHz)
  • Additive Output Jitter: 65fs_RMS (ADC SNR Method)
• LTC6953
  • JESD204B Subclass 1 SYSREF Signal Generation
  • Max. RF Frequency: 4.5GHz
  • Eleven Independent, Low Noise Outputs with Programmable Coarse Digital & Fine Analog Delays
  • Additive Output Jitter: <6fs_RMS (12kHz – 20MHz; 4.5GHz)
  • Additive Output Jitter: 65fs_RMS (ADC SNR Method)
• LTC6955/LTC6955-1
  • Max. RF Frequency: 7.5GHz
  • Eleven Ultralow Noise CML Outputs
  • Parallel Control for Multiple Output Configurations
  • LTC6955: 11 Output Buffer
  • LTC6955-1: 10 Buffered Outputs & One ÷2 Output

About Analog Devices
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