Motorola, Lucent Venture Unveils First DSP Core
By: Robert Keenan, Managing Editor
Just less than one year ago, Motorola and Lucent Technologies rattled the wireless industry when they jointly formed Star*Core (Atlanta, GA), which was set up to develop high-performance, low-power digital signal processor (DSP) cores for handsets and base station designs. After nearly a year of work together, Star*Core has released its first core, called the SC140.
As the wireless industry moves closer to third-generation (3G) technology, designers need to house more functionality in their base station or handset designs. Thus, they need products, such as DSP cores, that enable them to increase performance in their overall system design.
The 300 MHz SC140 has been designed to specifically meet these performance requirements. The new core delivers 3000 MIPS, or 1.2 billion multiply-accumulate (MAC), operations per seconds. This enables designers to perform more functions within the handset.
In addition to increasing functionality, handset designers are looking for products that consume less power so that they can develop systems that feature longer talk and standby times. The 300 MHz SC140 has also been designed to meet these requests. The new core operates at voltages down to +1.5 VDC. When operating at these supplies, the chip can consume as little as 0.1 mA/MIPS current when running at 300 MHz.
To lower consumption even further, system designers can implement a 120 MHz version of the SC140 in their handsets. This operates down to +0.9 VDC and consumes 0.066 mA/MIPS power.
The framework
The SC140 framework provides four MAC units, four arithmetic logic units (ALUs), four bit field units (BFUs), two arithmetic address units (AAUs), and a five-stage pipeline. Although it is based on a 16-b orthogonal instruction, the new core is designed to use variable-length execution sets (VLES). VLES technology allows multiple 16-b instructions and optional prefixes to be grouped together for single-cycle execution based on the opportunities identified in the specific code to be run on the DSP Core. Thus, the new core can perform 4 MAC instructions, 4 different ALU instructions, 4 bit manipulation instructions, or a combination of MAC, ALU, and bit manipulation instructions in one cycle.
Compiling and reuse
Star*Core claims that the SC140's computer-driven architecture allows designers to develop 90% of the software code required for a design in high-level programming languages, such as C or C++. In addition, the company says the core has been developed to promote reuse in future designs. Software written for the four-MAC SC140 can be leveraged for future SC100 implementations that may contain more or less resources.
Star*Core has released a set of baseline tools for the SC140. These tools include an assembler, an optimizer, a linker, a simulator, and a compiler. The baseline tools are available to customers under non-disclosure by Motorola and Lucent to support initial customer designs.
In addition, Star*Core has partnered with third-party vendors for tools that support the SC140 core and future SC100 family devices. The tools provided by these include Green Hills' MULTI environment, Embedded System Products' RTXC operating system, and ENEA OSE Systems' operating system.