Mentor Graphics And TSMC Collaborate On 65 Nanometer RF Design Kits
TSMC's 65nm mixed-signal and RF process offers both cost and performance advantages. The process is fully logic-compatible with both copper interconnect and low-K dielectrics on a 9-layer metal process with a core voltage of 1.2 volts and I/O voltages of 1.8, 2.5, and 3.3 volts. The 65nm RF design kit is a comprehensive kit covering both mixed-mode and logic sub-processes. It features devices such as High-Q inductors, MiM and Metal fringe capacitors, Deep N-Well isolation, and multiple Vt devices for added flexibility and coverage.
A packaged RF flow tutorial also accompanies the 65nm RF process design kit. This tutorial takes an RF circuit design from schematic capture through RF simulation, layout and post-layout simulation based entirely on the new 65nm RF PDK running on the ICStudio design platform with the Eldo RF simulator and the Calibre suite of tools. The tutorial encapsulates the flow between analog design tools, foundry process information and design methodology.
"Today's design technology can no longer be isolated from advancements in a foundry's process technology. Our close alliance with TSMC on design kit offerings is a fundamental part of Mentor's ongoing commitment to providing customers the most comprehensive design solution with strong confidence," said Jue-Hsien Chern, vice president and general manager, Deep Submicron (DSM) division.
"Our collaboration with Mentor continues the strategic focus of enabling high-performance, mixed-signal and RF designs. This release of the 65nm Mentor design kit after 90nm is evidence of our commitment," stated Kuo Wu, deputy director of Design Services Marketing at TSMC.
Mentor's new ICstudio custom IC design platform integrates all of Mentor's custom IC design tools into a seamless flow that enables designers to quickly and accurately conceptualize, capture, simulate, layout, and verify the most challenging custom, analog, RF, and mixed-signal designs.
SOURCE: Mentor Graphics Corporation