Large-Signal LDMOS Model Simulation Using Agilent Genesys Software

By Modelithics, Inc.

Overview

This application note guides the user through simulation of DC IV, S-parameters and swept power data of an LDMOS transistor (NEC NE5511279A) using Agilent Genesys software. An example Genesys workspace file is provided along with this note that can be used in reproducing the simulation results shown. The sample LDMOS model used in this application note is a Motorola-Electro-Thermal (MET) model extracted by Modelithics and validated against measured I-V, S-parameters, swept power and load-pull data. This model is used herein to demonstrate variety of simulation including single tone swept power simulations at different source and load impedances to show the effect of source and load match on output power, gain and power-added-efficiency. Measured data comparisons are included to add confidence to the quality of the simulation results. All measurement data shown was acquired by Modelithics, Inc.

Purpose

This app note is the first in a series of notes and tutorials intended to guide the user through the stages of simulation-based power amplifier design using Modelithics non-linear transistor models as well as high accuracy passive component models along with Agilent Genesys software. This note covers the initial phase of installing the non-linear transistor model, simulating DC I-V curves, S-parameters and swept power data with different impedances presented to the active device. Subsequent notes will cover simulation of load-pull power and efficiency contours, and design of the input and output matching network to optimize power for a single stage class AB PA.