Bias Control Of LDMOS Devices In RF Power Amplifiers

Terry Millward
Maxim Integrated Products

Introduction
LDMOS FET technology has emerged as the leading technology for high power RF applications, especially for base station power amplifiers for cellular systems. Breakdown voltages of 65 V or higher allow use with a 28 V supply while retaining ruggedness and reliability. This article outlines the characteristics of these devices and describes various methods of biasing to obtain best performance.

LDMOS characteristics
The LDMOS (laterally diffused metal-oxide-semiconductor) FET structure is shown in Figure 1. It is a three-terminal device with a p-type semiconductor substrate into which n source and drain regions are formed. There is a laterally diffused low resistance p "sinker" connecting the source region to the p substrate and source terminal. This means that the substrate can be directly soldered to the RF ground, minimizing the effects of wiring parasitics. The gate region is isolated from the conducting channel by the thin layer of SiO2. When a positive voltage is applied to the gate with respect to the source, an inversion layer (or channel) is formed between the two n-type regions allowing current to flow between the drain and source. An LDMOS FET operated in the "enhancement-mode." With a positive drain voltage (with respect to the source), no drain current flows until a positive gate voltage enhances a channel across the p well. When used as an amplifier the channel current is modulated by an AC signal mixed with the gate bias voltage. Figure 2 shows the typical relationship between drain current and gate voltage at various temperatures. Note that other RF devices, GaAs FET, and MESFET require a negative bias voltage with respect to the source.

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Figure 1

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Figure 2

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