Downloads


Application Note: Connected Simulation And Test Solutions Using The Advanced Design System

Agilent EEsof EDA

File Size: 5.43 MB   Estimated Download Time: < 1 min
Description

Designing and verifying designs to today's complex signal formats can present some interesting challenges. Designs can be verified in simulation and they can later be verified after all of the hardware returns from fabrication -- but an intermediate level of verification early in this design/fabrication cycle can be difficult to achieve because it may require all, or most of, the prototype hardware. Fabrication cycle time often results in inefficiencies while designers wait for hardware before performing verification testing. Add a couple of design iterations to this, and design time really adds up.

Some typical problems are:

  • The hardware returns from fabrication and the system does not meet the original design specifications. Isn't there a way to evaluate system level performance even earlier with partial hardware, to help minimize risk and costs?
  • I use my design tool in the simulation/design phase, then transition to test equipment for the testing phase. How can I get more consistency between my design and test solutions for better design predictability? How can I transition back into my design tool for design modifications if the hardware is not performing correctly on the test bench?
  • I'd like to begin Bit Error Rate testing of my RF hardware, but it requires baseband functionality, which isn't available yet. How can RF testing begin before the baseband sections are done?
  • I can test components with "ideal" signals, but how can I evaluate my DUT (Device Under Test) with custom test signals that reflect how the component will be used in the system?
  • How can I evaluate re-using hardware with a new signal format or new design modeled in simulation before building all of the hardware? How do I test hardware if the new signal format isn't available as a test solution?

Agilent EEsof EDA

More From Agilent EEsof EDA

Please wait... busy

Send This Page To An Associate: