APLAC® Simulator

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AWR acquired APLAC in 2005 and has since integrated this world class, foundry-approved harmonic balance / transient circuit simulation engine into its product portfolio. Today this technology is only available within AWR design suites.

The APLAC simulation engine has been used in Nokia product development for more than a decade now as its enhanced harmonic balance method enables simulation of larger RFIC circuits faster and with less memory.

The APLAC simulator offers multi-level analyses which includes:

• DC operation point
• Linear frequency domain
• Time domain
• Harmonic balance
• Phase noise
• Linear/non-linear noise including AC noise contributors, temperature
• Yield predictions and optimization