White Paper: Practical Analysis Of Backplane Vias

By Dr. Eric Bogatin of Bogatin Enterprises, Lambert Simonovich of Nortel, and Sanjeev Gupta and Mike Resso, of Agilent Technologies

In this paper, Dr. Bogatin and his co-authors show how accurate, verified models for vias in a multilayer circuit board are necessary to predict link performance in the multi-gigabit-per-second regime. It describes a method for using measurements on a test vehicle to build a high-bandwidth, scalable model of long vias, including the through- and stub-effects. This model can then be used in Agilent's Advanced Design System for simulation. The methodology provides valuable insight into the root causes of performance limits and how to overcome them.

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