CST BOARDCHECK – PCB Rule-Checking ProgramSource: CST of America, Inc.
CST BOARDCHECK™ analyzes printed circuit boards (PCB) with respect to electromagnetic compatibility (EMC) and signal integrity (SI) design rules, highlighting the potential problems in their layout. Popular layout formats such as CADENCE® ALLEGRO®, Zuken CR 5000, Mentor Graphics® Expedition®, and ODB++ can be imported.
With the ability to examine each critical net and component in a PCB individually, CST BOARDCHECK removes the risk of human error in ensuring that EMC or SI design rules are not violated. A report listing all violations can be viewed graphically or in HTML format and allows users to easily identify potential problems within the design.
The EMC design rules can identify potential problems with:
- Net reference
- Component placement
The SI design rules meanwhile ensure:
- Net integrity
- Via integrity
The EMC performance of a PCB is primarily based on the location of components and the location of various critical and I/O nets. CST BOARDCHECK can be included cost-effectively in the design process, addressing layout problems early on and allowing regulatory requirements to be met immediately.