Articles


High Performance SI/PI Solutions Workshop - February 1, 2010 In Santa Clara, CA

January 21, 2010

Request Information
High Performance SI/PI Solutions Workshop - February 1, 2010 In Santa Clara, CA

You are invited to our brand new "High Performance" workshop series focusing on getting designs to market faster.

The launch workshop for this series is on Monday February 1, 2010 at the Hyatt Regency hotel in Santa Clara . This is a FREE , half day, AM workshop and all DesignCon attendees and other interested parties are invited to attend.

  • 8:45-9:00:  Introduction to CST's high performance solutions,  CST
  • 9:00-9:30:  Fast solutions for power integrity analysis, CST
  • 9:30-10:00:  Guest speaker, TBD
  • 10:00-10:30:  High speed serial link channel modeling, Gerardo Romo, CST
  • 10:30-11:00 :  Break and refreshments
  • 11:00-11:30 :  Cable interference and immunity/emissions analysis, CST
  • 11:30-12:00:  Guest speaker – Albert Wallash, Hitachi
  • 12:00-12:30:  New developments in EDA/SI/PI simulation, Peter Thoma, CTO CST

For more details and to register please go to:

www.cst.com/Content/Events/Details.aspx?eventId=1460

This event will roll out across North America in April and May. Locations to include, Phoenix, AZ, Los Angeles, CA, Waltham, MA, Ottawa, QB, Dallas, TX, Denver, CO, Chicago, IL, Dayton, OH, Arlington, VA, Vancouver, BC and Hillsboro, OR. More details to follow.

DesignCon 2010, Santa Clara , CA

Please stop by our booth near the entrance to see a demo of our brand new 2010 release or come to one or more of our collaborative conference papers to see how we are helping customers explore new and novel designs through 3D simulation.  

Tuesday, February 2, 2:50-3:30 PM "Chip-to-Chip Communication Beyond 25 Gbps: Modeling and Realization" Jianmin Zhang, Qinghua Bill Chen, Kelvin Qiu, Cisco. Martin Schauer, Antonio Ciccomancini Scogna, and Gerardo Romo, CST of America Inc. 

Wednesday, February 3, 2:00-2:40 PM "Efficient Modeling and Simulation for Package-PCB Co-Design and Co-Optimization"Martin Schauer, CST of America .  Hong Ahn, Namhoon Kim, Chris Wyland, Paul Wu, Xilinx.

Thursday February 4, 9:50-10:30 AM "Full-Wave Time Domain Modeling of Interconnects" Martin Schauer, CST of America Inc.  Alfred Neves, Tom Dagostino, Scott McMorrow, Teraspeed Consulting LLC

More details can be found here.

SOURCE: CST of America®, Inc.

CST of America®, Inc.

More From CST of America®, Inc.

Please wait... busy