Articles
White Paper: Advanced Chip Scale Packaging Technology
June 26, 2008
Introduction
Smaller, lower cost components are crucial to the development of today's higher-performance, smaller and increasingly price-competitive mobile devices. Since the introduction of chip scale packages (CSPs) they have become a major trend in active device packaging. Chip scale packaging combines the size and performance advantage of bare die assembly and the reliability of encapsulated devices, while permitting automated assembly processes and low production costs.
Chip Scale Packages
According to the IPC/JEDEC J-STD-012 definition, a chip scale package is a single-die, surface-mountable package with an area of no more than 1.2 times the area of the original die. This definition is somewhat fluid, since, for example, there have been cases of original die being shrunk due to process changes and improvements with customers requiring that the resulting CSP be unchanged. There are also multi-layer CSPs that incorporate several stacked active devices. There is no overall definition of how a chip-scale package is to be constructed, so any package that meets the surface-mounting and dimensional requirements of the definition is a CSP. Click Here To Download:•White Paper: Advanced Chip Scale Packaging Technology
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